Integrating network using at least one D-C amplifier

ABSTRACT

An integrating network for performing integration of an input voltage by the use of an integrator comprising time-constant means and a d-c amplifier, wherein a drift memory circuit is provided between the output and input of the integrator for feeding back from (in the opposite polarity) from the output of the d-c amplifier to (the) an input terminal of the integrator, a feedback signal of polarity in opposition to the input voltage in a case of no input of the d-c amplifier so as to obtain a stationary condition and for continuously sending out, as a feedback signal, a voltage fed back to the input of the integrator at the stationary condition, the feedback signal having a value substantially equal to the drift voltage of the dc amplifier converted in terms of the input of the d-c amplifier, whereby an input voltage is integrated in the integrating network without error caused by the drift of the d-c amplifier.

United States Patent 1191 Uchida [11] E Re. 28,579

[ 1 Reissued Oct. 21, 1975 1 1 INTEGRATING NETWORK USING AT LEAST ONED-C AMPLIFIER [75] Inventor: K010 Uchida, Tokyo, Japan [21] Appl. No.:474,806

Related U.S. Patent Documents [58] Field of Search 307/297, 229, 238;328/127, 328/128; 330/9; 235/183 56] References Cited UNITED STATESPATENTS 3,070,786 12/1962 Maclntyre 307/297 3,072,856 l/1963 Close328/127 3,147,446 9/1964 Wittenberg 330/9 Va :4 R 2 10 3,167,718 1/1965Davis et al 307/229 3,246,171 4/1966 White r 307/229 3,382,461 5/1968Wolcott 330/9 3,541,320 11/1970 Beall 330/9 OTHER PUBLICATIONS AutomaticDrift Compensation in DC. Amplifier, by Cederbaum, et. al., pp. 745-747,Rev. of Sci. Inst., August, 1955, Vol. 26, No. 8.

Primary Examiner-Michael J. Lynch Assistant Examiner-B. P. DavisAttorney, Agent, or FirmRobert E. Burns; Emmanuel J. Lobato; Bruce L.Adams [57] ABSTRACT An integrating network for performing integration ofan input voltage by the use of an integrator comprising time-constantmeans and a d-c amplifier, wherein a drift memory circuit is providedbetween the output and input of the integrator for feeding back [in theopposite polarity] from the output of the d-c amplifier to [the] aninput terminal of the integrator, a feedback signal of polarity inopposition to the input voltage in a case of no input of the d-camplifier so as to obtain a stationary condition and for continuouslysending out, as a feedback signal, a voltage fed back to the input ofthe integrator at the stationary condition, the feedback signal having avalue substantially equal to the drift voltage of the d-c amplifierconverted in terms of the input of the d-c amplifier, whereby an inputvoltage is integrated in the integrating network without error caused bythe drift of the d-c amplifier.

21 Claims, 16 Drawing Figures Reissued Oct. 21, 1975 Sheet 1 of9 Re.28,579

Reissued 0a. 21, 1975 Sheet 2 of9 Re. 28,579

Reissued Oct. 21, 1975 Sheet 3 of9 Re. 28,579

Reissued Oct. 21, 1975 Sheet 5 of9 Re. 28,579

25 f Y 27 PULSE GENERATOR COUNTER a 23 J a 1 s A 1 2 I i LEVEL i iDETECTOR I Reissued 0m. 21, 1975 Sheet 6 0f 9 Re. 28,579

Q LI

fob

Fig. 12

Reissued Oct.2l, 1975 Sheet? of9 Re. 28,579

25 2a" 27 P U L 5 E A C OUN TE R GENERATOR 4a f F MULTI- 5 V/BRATOR 5SWITCH CONTROL CIRCUIT Reissued Oct. 21, 1975 Sheet 8 of9 Re. 28,579

Fig. 15

Reissued Oct. 21, 1975 Sheet 9 of9 Re. 28,579

COUNTER PULSE GENERATOR I I I l l l I I P 1 0 I ll.

VIBRA TOR SWITCH CONTROL CIRCUIT Fig. 16

INTEGRATING NETWORK USING AT LEAST ONE D-C AMPLIFIER Matter enclosed inheavy brackets 1 appears in the original patent but forms no part ofthis reissue specification; matter printed in italics indicates theadditions made by reissue.

This invention relates to integrating networks having an output waveformcorresponding to the time integral ofits input waveform and moreparticularly to integrating [network] networks using at least onedirectcurrent amplifier.

In conventional integrating networks for obtaining an integrated valuecorresponding to the time integral of the input signal, a d-c amplifieris usually used. In this case, stability and no-drift are required ofthe d-c amplifier since an integrating error is caused by the drift. Toreduce the value of the drift, chopper amplifiers are frequently used.However, the drift is still appreciable in the chopper amplifier, sothat the value of drift is a main factor for determining the precisenessof integration. The above-mentioned drift can be eliminated bydrift-compensation which is manually carried out for zero adjustment.However, it is very troublesome to perform such manual adjustment atevery integration. Moreover, it is very difficult to always obtaincorrect results by [the] manual adjustment.

An object of this invention is to provide integrating networks capableof eliminating the above-mentioned defects of the conventional art andcapable of readily performing zero adjustment with certainty.

Another object of this invention is to provide integrating networkssuitable for highly reliable analoguedigital converters.

In accordance with the feature of this invention, there is proposed anintegrating network for performing integration of an input voltage bythe use of an integrator comprising time-constant means and a d-camplifier, characterized in that a drift memory circuit is providedbetween the output and input of the integrator for feeding back [in theopposite polarity from the output of the d-c amplifier to [the] an inputter minal of the integrator, in a case of no input of the d-c amplifier,afeedback signal of polarity in opposition to the input voltage so as toobtain a stationary condition, and for continuously sending out, asafeedback signal. a voltage fed back to the input of the integrator atthe stationary condition, the feedback signal having a valuesubstantially equal to the drift voltage of the d-c amplifier, wherebyan input voltage is inte grated in the integrating network without errorcaused by the drift of the d-c amplifier.

The principle, construction, operation and merits of this invention willbe better understood from the following more detailed discussion inconjunction with the accompanying drawings, in which similar parts aredesignated by the similar reference numerals, characters and symbols,and in which:

FIG. I is a waveform diagram explanatory of drift in a d-c amplifierused in this invention;

FIG. 2 is a block diagram illustrating an embodiment of this invention;

FIG. 3 is a block diagram illustrating a modification of the embodimentshown in FIG. 2;

FIGS. 4, 5, 6 and 7 are block diagrams each illustrat ing an embodimentof this invention;

FIG. 8 is a waveform diagram explanatory of the effect of drift in a dcamplifier used in an analoguedigital converter using an integratingnetwork of this invention;

FIGS. 9, l1 and 14 are block diagrams each illustrating an example ofthe invention suitable to form an analogue-digital converter;

FIGS. l0, l3 and 16 are block diagrams each illustrating ananalogue-digital converter using an integrating network of thisinvention;

FIGS. 12 and 15 are time charts explanatory of operations of theexamples shown in FIGS. II and 14.

With reference to FIG. I, the concept of how an integration error iscaused by the drift in a d-c amplifier used in an integrator is at firstdescribed. If it is assumed that the voltage of an input signal and thetime constant of an integrator are values V, and RC respectively, anoutput waveform V having the gradient (V /RC) is obtained at the outputof the integrator in response to the voltage V; of the input signalapplied if the d-c amplifier employed in the integrator has no drift. Inthis case, the output waveform V would reach a voltage V,,, equal to avalue (V,.t/RC) at a time T delayed by a time t after a time T, when theoutput waveform V exceeds a predetermined reference level (e.g.; zerolevel Lo).

However, if the d-c amplifier drifts, the output waveform V would reacha value (Vd.t,/RC) at the time T even if the voltage V, of the inputsignal is zero; where the value Vd is a value of drift converted interms of the input of the integrator. Accordingly, if the input voltageV. of the input signal is applied to the integrator having the drift Vd,the output waveform V has the gradient (Vi Vd)/RC and reaches a valueVoa =(V, Vd)t /RC at the time T, delayed by the time t, after the timeT,, when the output waveform V exceeds the zero level Lo. In otherwords, an error [(Voa- Vo)l](V0a- Vol) equal to a valueVd.t /RC is aresult of the drift Vd.

As mentioned above, drift is a main factor of error in the conventionalintegrating network. To reduce the error to a minimum, an amplifier(e.g.; chopper amplifier) having only a small drift has been employed,However even with such a provision, the elimination of errors is notsufficient while the cost of the integrating network is relatively high.

In accordance with the principle of this invention, a compensatingvoltage Vd is continuously applied to the input of the integrator inaddition to the input voltage Vi of the input signal before everyintegration if the value of drift converted in terms of the input of theintegrator is a value Vd. As a result of this feature of this invention,the drift can be effectively eliminated without use of an expensivechopper amplifier to provide a reliable integrator of low cost.

With reference to FIG. 2, an embodiment of this invention comprisesinput terminals 1 and 2 for applying an input signal to be integrated, aswitch 3 connected between a common terminal 7 and one of two terminals4 and 5, an integrating register 8, an integrating capacitor 9, a d-camplifier 11 having a sufficient gain and producing an output whosepolarity is reverse to the polarity of the input signal applied to theinput 10 of the amplifier 11, an output terminal 12, a switch 13, acapacitor 14, a field-effect transistor I6 having a gate IS, a resistor17 applying a necessary voltage between the drain and source of thefield effect transistor 16 from d-c power terminals +8 and B, and aconnection line 18 connecting the source of the field-effect transistor16 to the terminal 4 of the switch 3. The integrating resistor 8, theintegrating capacitor 9 and the d-c amplifier 11 form an integrator. Thecapacitor 14, the field effect transistor 16 and the resistor 17 forms adrift memory circuit as understood from the following description.

In this embodiment shown in FIG. 2, if it is assumed that a value ofdrift converted in terms of the input of the integrator is a value Vd,this converted drift is equivalently applied across the common terminal7 and the ground potential. In this case, if the common terminal 7 ofthe switch 3 is connected to the terminal 4 so as to make the inputsignal V,- zero at the common terminal 7, a current Vd/R flows throughthe resistor 8 having a resistance R so that the capacitor 9 (having acapacitance C) is charged. The output wave form V obtained at the outputterminal I2 is a linear wave form having the gradient Vd/RC'. Therefore,when this in tegrating network attains a stationary condition afterconnection between the terminals 4 and 7 and switchin of the switch 13,respective potentials of the input 10 of the amplifier 11 and theconnection line 18 are equal to each other so that no current flows inthe resistor 8. In this case, the potential to ground of the connectionI4 is a voltage which causes the potential Vd to the ground of theconnection line 18.

In this connection, after the switch 13 is switched-off and theterminals 5 and 7 are connected to each other, the input signal V, isapplied across the terminals I and 2. Since the potential to ground ofthe input terminal 2 is a value -Vd due to the charged voltage of thecapacitor 14, a current i which is obtained by dividing, by theresistance R of the resister 8, the sum of the potential to ground -Vdof the terminal 2, the value of drift Vd converted in terms of the inputterminal and the input signal Vi flows through the resister 8. Namely:

Accordingly, a linear waveform having the gradient Vi/RC is obtained atthe output terminal 12 as an output voltage Vo. At a time T, delayed bya time t, from a time T, when the output voltage V0 exceeds the zerolevel Lo, the output voltage Vo reaches a value -Vi.t /RC.

As mentioned above, a highly reliable integrator can be provided bydetecting the drift Vd converted in terms of the input terminal beforethe performance of integration and by compensating the drift of theintegrator by the use of the detected drift value.

lfa chopper amplifier etc. having a limited small drift is employed asthe d-c amplifier 11, the preciseness of integration of the integratorraises further. The switches 3 and 13 may be formed by a desired type,such as mechanical switch or electronic switch.

In order to reduce [a] the detecting-and storing time necessary todetect and store the drift value after connection between the terminals4 and 7 at the switch 3, namely [a] the time necessary to reach [the] astationary condition in a loop (terminals 4 and 7 the resistor 8 theamplifier 11 the switch 13 the field-effect transistor 16), theintegrating capacitor 9 may be disconnected from the input or output ofthe amplifier 1] at the detecting-and-storing time.

In the embodiment shown in FIG. 2, the field-effect transistor [6 isconnected as a source follower. However, this source follower may bereplaced by an amplifier or an attenuator. Moreover, an amplifier or anattenuator may be inserted between the output of the d-c amplifier 11and the output terminal 12. These embodiments will be successivelydescribed below in detail.

The switch 3 maybe inserted between the integrating resistor 8 and theinput 10 of the d-c amplifier 11 as shown in FIG. 3. In this embodiment,operations similar to the embodiment shown in FIG. 2 can be performed.

In these embodiments, if necessary a resistance may be inserted in theconnection line 18.

As mentioned above, the sum (Vi e Vd) of the input signal Vi and theoutput (Vd) of the drift memory circuit is applied during the time t, tothe input of the inte grator so that the drift Vd is compensated.Accordingly, if the stability of the integrator and the drift memorycircuit is sufficient during the time t,, an error of integration causedby drift which continues also after the time t can be completelyeliminated. Moreover, since a d-c amplifier having an extremely smalldrift is not an essential means, the integrating network of thisinvention can be formed at low cost.

In the above-mentioned embodiments, if an active circuit is connected atthe preceding stage of the integrating network, the apparent voltage ofa d-c power source of the preceding active circuit is equivalent to thesum of the voltage (+B) of the d-c power source and the converted driftvoltage (Vd) in the feedback signal. Accordingly, a separate d-c powersource is necessary.

With reference to FIG. 4, an embodiment of this invention which does notrequire a separate d-c power source of the preceding stage even if anactive network is connected to the preceding state will be described. Inthis embodiment, a differential amplifier lla having two [inputs] inputterminals 10a and 10b is employed in place of the d-c amplifier 11having the single input 10 in the embodiments shown in FIGS. 2 and 3.Moreover, a d-c amplifier I9 having a single input is employed in placeof the source follower of the embodiments shown in FIGS. 2 and 3. Thedifferential amplifier lla has [a sufficient 1 an amplification factor uand the polarity of the input terminal 10a is reverse to the polarity ofthe output terminal 12 of the amplifier lla while the I. The polarity ofthe input terminal 10b is the same as the polarity of the outputterminal of the amplifier 11a. The d-c amplifier 19 has an amplificationfactor u and the polarity of the input terminal of this amplifier I9 isreverse to the polarity of the output terminal thereof. The d-camplifier 19, a switch 13 and a capacitor 14 form a drift memory circuit20 which feeds back the output signal of the differen rial amplifier 110I0 the other input terminal lOh therenfin the same polarity us thatofthe input terminal as mentioned above. A converted drift voltage asmentioned below is applied to the input 10b through a connection line183 from the drift member circuit 20. The terminal 4 of the switch 3 isgrounded, while other parts are the same as the parts of the embodimentsshown in FIGS. 2 and 3.

In operation, the common terminal 7 of the switch 3 is connected to theterminal 4 while the switch I3 is switched-on. In this case, ifit isassumed that respective drift voltages of the amplifiers 11a and 19converted in terms of the respective inputs are a value V, (at the inputterminal a) and a value V the output voltage V of the output terminal I2is as follows:

mlvgug v l.

Therefore, a voltage V 2 of the input terminal 10b becomes equal to theconverted voltage V, so that no current flows in the resistor 8. In thiscase, a quiescent condition is established.

Thereafter, when the switch 13 is switched-off while the common terminal7 of the switch 3 is connected to the terminal 5, an input voltageapplied across the terminal I and the ground is integrated by anintegrator formed by the integrating resister 8, the differentialamplifier 11a and the integrating capacitor 9. In this case, since thevoltage V, of the input terminal 10b is still maintained at the voltageV the drift of the differential amplifier lla can be effectivelycompensated. Accordingly, the integration of the input voltage can beperformed without error caused by drift" in the integrator. In the aboveoperation, if the drift voltages V and V are not varied, the gradient ofthe integrated output voltage V is irrespective of the drift voltages Vand V so that drift" is completely eliminated from this integratingnetwork. In this case, if an input voltage V, is applied across theinput terminal 1 and the ground, an output voltage V having the gradientV lRC can be obtained at the output terminal 12.

In the drift memory circuit of the embodiment shown in FIG. 4, theswitch 13 and the capacitor 14 may be provided before the d-c amplifier19 as shown in FIG. 5. In this case, the charged voltage of thecapacitor 14 is amplified at the d-c amplifier l9 and applied to theinput terminal 10b of the differential amplifier lla through theconnection line 18a. Other parts are the same as the parts of theembodiment shown in FIG. 4. In this embodiment, the dc amplifier 19 hasto have a high impedance sufficient for avoiding a short-time dischargeof the charged voltage of the capacitor 14. If the amplification factorn of the d-c amplifier 19 is sufficiently large, the above-mentionedEquation (3) is converted as follows:

Therefore, the drift voltages in the amplifiers Ila and I9 areeffectively eliminated.

With reference to FIG. 6, a modification of the embodiment shown in FIG.4 will be described. In this embodiment, a d-c amplifier 21 having anamplification factor u is provided between the switch 3 and theintegrating resistance 8. Other parts are the same as the parts of theembodiment shown in FIG. 4.

In operation, the common terminal 7 of the switch 3 is connected to theterminal 4 while the switch 13 is switched-on. In this case. if it isassumed that respective drift voltages of the amplifiers 21, 11a and I9converted in terms of the respective [inputs] input terminals are avalue V,, a value V; (at the input terminal 103) and a value V theoutput voltages V of the output terminal 12 is as follows:

Ifa condition u,u I is applied to the Equation (5 l, the followingresult is obtained.

In this case, if it is assumed that the voltage of the input terminal10a is a value V the voltage of the input terminal 10b can be indicatedas follows:

If conditions u u 1 and n I are applied to the Equation (7), thefollowing result is obtained.

Therefore, no current flows in the resistor 8.

Thereafter, when the switch 13 is switched-off while the common terminal7 of the switch 3 is connected to the terminal 5, an input voltageapplied across the terminal l and the ground is integrated by anintegrator formed by the d-c amplifier 21, the integrating resistor 8,the differential amplifier lla and the integrating capacitor 9. In thiscase, since the voltage V, of the input terminal 10b is still maintainedat a voltage Vd equal to a voltage (V u V the drift voltages ofthedifferential amplifier Ila and the d-c amplifier 21 can be effectivelycompensated. Accordingly, the integration of the input voltage can beperformed without error caused by drift in the integrator. In the aboveoperation, if the drift voltages V,, V and V are not varied, thegradient of the integrated output voltage V,, is irrespective of thedrift voltages V,, V and V so that drift is completely eliminated fromthis integrating network. In this case, if an input voltage V is appliedacross the input terminal 1 and the ground, an output voltage V, havingthe gradient V /RC can be obtained.

In the drift memory circuit 20 of the embodiment shown in FIG. 6, theswitch 13 and the capacitor 14 may be provided before the d-c amplifierI9 as shown in FIG. 7. In this case, the charged voltage of thecapacitor 14 is amplified at the do amplifier l9 and applied to theinput terminal 10b of the differential amplifier 11a through theconnection line 18a. Other parts are the same as the parts of theembodiment shown in FIG. 6. In this embodiment, the d-c amplifier 19 hasto have a high impedance sufficient for avoiding a short-time dischargeof the charged voltage of the capacitor 14. If the amplification factoru of the amplifier 19 is sufficiently larger than one and alsosufficiently larger than the amplification factor u of the amplifier 2],the above Equation (6) is converted as follows:

Therefore, the drift voltages in the amplifiers 21, Ila and 19 areeffectively eliminated.

Each one of the above-mentioned integrating networks of this inventioncan be applied to form an analogue-digital converter in which an inputsignal is inte grated to detect the level of the input signal. Adetailed discussion of the analogue-digital converter will follow aftera description of how an error is caused by the drift in the integrator,described in view of the principle of the analogue-digital converterwith reference to FIG. 8.

If it is assumed that the voltage of an input signal, a referencevoltage and the time constant of the integrator are respectively valuesV V, and RC, an output wave form V,, having the gradient (-VJRC) isobtained at the output of the integrator in response to the voltage V ofthe input signal if the d-c amplifier employed in the integrator has nodrift. In this case, if the input of the integrator is switched to thereference voltage V, at a time T, delayed by a time t, after a time T,when the output wave form V,, exceeds a predetermined reference level(e.g.; zero level Lo). the gradient of the output wave form V varies toa value V,,/RC so that the output waveform V reaches the zero level Loat a time T, delayed by a time t, from the time T In this case. thefollowing result is obtained.

Accordingly, the voltage V, of the input signal can be obtained from thevalues t lt, and V,,. This is the general principle of an analog-digitalconverter.

However. if the dc amplifier drifts, the output waveform Vo would reacha value (Vd.t,/RC) at a time T, even if the voltage V, of the inputsignal is zero; where the value Vd is a value of drift converted interms of the input of the integrator. Accordingly, if the input voltageV, of the input signal is applied to the integrator having the drift Vd,the output wave form Vo has the gradient V, Vd)/RC. Therefore, if theinput of the integrator is changed to the reference voltage V, at thetime T, delayed by the time t, from the time T, when the output waveformVo exceeds the zero level L0. The following error (t t results from thedrift Vd.

FIG. 9 shows main parts of the analogue-digital converter using theintegrating network of this invention to perform the above-mentionedprinciple without drift error." In this example, a terminal 6 is furtherprovided at the switch 3 while a separated d-c source 22 is connectedacross the line 18 and the terminal 6. Other parts are the same as theintegrating network shown in FIG. 2.

In operation, a linear wave form having the gradient V /RC is obtainedat the output terminal 12 as an output voltage V,,, in a manner similarto the operation of the integrating network shown in FIG. 2. At a timeT, delayed by a time t, from the time T, when the linear wave formexceeds a predetermined reference level (e.g.; zero level Lo), theterminal 6 and the terminal 7 are connected to each other at the switch3 while the switch 13 is maintained at the switched-off condition. Sincethe polarity of the reference voltage V, is reverse to the polarity ofthe input voltage V,, a current i, which is obtained by dividing, by theresistance R of the resistor 8, the sum of the potential to the groundVd of the line 18, the reference voltage V, of the reference d-c source22 and the value of the drift Vd converted in terms of the inputterminal of the integrator flows in the resistor 8. Namely:

Accordingly, a linear wave form having the gradient V,,/RC is obtainedat the output terminal 12. At a time T delayed by a time t: from thetime T the output voltage V reaches the zero level Lo. In this case, therelationship shown in the Equation is obtained. After the time T theswitch I3 is switched-off while the terminal 4 and the terminal 7 areconnected to each other at the switch 3 so that the above-mentionedstationary condition is obtained. Thereafter, these operations arerepeated.

As understood from the above explanation. the relationship shown in theEquation (l0) can be obtained without error caused by "drift" even ifthe integrator has drift."

With reference to FIG. 10, an example of the analogue-digital converterprovided with means for measuring the value t,/t shown in the Equation(l0) comprises input terminals 1 and 2, a switch 3, an integrator 23, aswitch 13, a drift member circuit 20, a reference d-c source 22, azero-level detector 24 generating control pulses when the output voltageof the integrator 23 reaches a reference level (e.g.; zero level), apulse generator 25 generating pulses at regular intervals, a counter 26counting the number of the pulses applied from the pulse generator 25,and an output terminal 27.

In operation. if the drift voltage of the integrator 23 converted interms of the input thereof is a value Vd when the switch 13 isswitched-on while the terminal 4 is connected to the terminal 7, theoutput of the drift memory circuit 20 is maintained at a stationaryvalue Vd. After an appropriate time in which the above stationarycondition continues, the switch 13 is switchedoff while the terminal 5is connected to the terminal 7 at the switch 3. Since the input voltageV,- is applied across the terminals 1 and 2 and the potential to groundVd is applied to the terminal 2 from the drift member circuit 20, thepotential to ground of the input (e.g.; terminal 7) of the integrator 23becomes a value V, V On the other hand, the drift voltage V,, of theintegrator 23 converted in terms of the input thereof is a value VAccordingly, the output voltage V, of the integrator 23 obtained at theterminal 12 has the following gradient:

This output voltage V, is applied to the zero level detector 24, so thata first reset pulse is applied from the zero level detector 24 to thecounter 26 at a time T, when the output voltage V, reaches the zerolevel Lo. In response to the first reset pulse, the counting state ofthe counter 26 is reset to a first counting state corresponding to afirst number. Thereafter, the counter 26 counts the number of pulsesfrom the pulse generator 25. When the counting state of the counter 26reaches a second counting state corresponding to a second number, thecounter 26 generates a second reset pulse which is applied to the switch3 so as to switch the terminal 7 to the terminal 6. At the same time,the counter 26 is reset to zero. The second reset pulse is generated atthe time T, delayed by the time t, from the time T,,. After the time T,,the voltage V, is applied across the line 18 and the terminal 7 so as tobe reverse to the polarity of the input voltage V the output voltage Vat the terminal 12 has the following gradient:

At the time T delayed by the time t from the T,. the output voltage V ofthe integrator 23 reaches the zero level Lo so that the zero leveldetector 24 generates a control signal. This control signal is appliedto the switch 3 to switch the terminal 7 to the terminal 4 and to theswitch 13 to switch it "on." The number of pulses counted in the counter26 during the time t, is proportional to the input voltage V,. Thiscounting result is obtained at the output terminal 27. In response tothe switching of the switches 3 and 13, the drift memory circuit 20starts to detect and store the drift voltage Vd of the integrator 23,and the abovementioned operations are repeated.

Another embodiment of the integrating [networks network of thisinvention to be employed for providing an analogue-digital converter isdescribed with reference to FIG. 11. In this embodiment, a d-c amplifierllb is further provided at the output of the integrator (8, 9 and lla).The output terminal 12 is provided at the output terminal of the d-camplifier 11b, and the input of the drift memory circuit 20 is connectedto the output terminal of the d-c amplifier llb. Moreover, a groundedterminal 6 is provided at the switch 3 and a reference voltage source 22is connected across the terminal 4 of the switch 3 and ground. Otherparts are the same as the parts of the embodiment shown in FIG. 4.

In operation, the common terminal 7 of the switch 3 is connected to theterminal 6 while the switch 13 is switched-on. In this case, if it isassumed that the respective drift voltages of the d-c amplifiers lla,llb and 19 converted in terms of the respective [inputs input terminalsare values V,, V and V;,, the output voltage V of the output terminal 12is as follows:

where references u u and u are respective amplification factors of theamplifiers 11a, llb and I9. lfa condition u,u u I is applied to theEquation (IS), the following result is obtained.

Therefore, a voltage V of the input terminal of the amplifier 11!) isindicated as follows:

If a condition u u u I is applied to the Equation [7), the followingresult is obtained.

Moreover, a voltage V 2 of the input terminal 10b of the amplifier I lais indicated as follows:

z zl trt a a l a s i i+ zl- If a condition u u u I is applied to theEquation (19), the following result is obtained.

Since the amplification factor u, is sufficiently larger than one, thefollowing Equation (2|) is substantially satisfied.

Accordingly, no current flows in the resister 8. In this case, aquiescent condition is established. Thereafter, the switch 13 isswitched-off and the terminal 7 of the switch 3 is switched to theterminal 5 to integrate, in the integrator (8, 9 and Ila), the inputvoltage V, applied across the terminal 5 and the ground. In this case,the integrator performs the integration of the input voltage V, withouterror caused by the drift of the amplifier lla as understood from theEquation (20). Moreover, the integrated result is obtained at the outputterminal after amplification by the amplifier llb without error causedby the drift of the amplifier llb as understood from the Equation (18).

With reference to FIGS. 12 and 13, an example of the analogue-digitalconverter using the integrating network shown in FIG. 11 will bedescribed. In addition to parts shown in FIG. 11, this example furthercomprises a multivibrator 24a reversing the state thereof when theoutput W2 of the amplifier llb intersects with a reference level 0, anda switching control circuit 28 for controlling the switches 3 and 13 inresponse to control signals from the multivibrator 24a and the counter26. The pulse generator 25 and the counter 26 are the same as thecircuits 25 and 26 of the example shown in FIG. 10. The d-c amplifierllb and the multivibrator 2421 form a zero-level detector 29.

In operation, a stationary condition is obtained in a condition wherethe switch 13 is switched-on and the common terminal 7 of the switch 3is connected to the grounded terminal 6. At a time T the switch 13 isswitched-off while terminal 7 is switched to the terminal 5 in responseto the control signal supplied from the switch control circuit 28.Accordingly, a waveform W2 is obtained at the output terminal of theamplifier llb in response to the input signal V applied across the inputterminal 1 and the ground. At a time T when the instantaneous level ofthe waveform w exceeds the zero-level O. the state of the multivibrator24a is reversed. In response to the change of state of the multivibrator 24a, the counter 26 starts to count the number of pulses fromthe pulse generator 25. At a time T delayed by a time t, from the timeT,,, the counter 26 counts over n pulses so that the counter I: 26a] 26is reset and generates a control signal which is applied through a line33 to the switch control circuit 28. In response to the control signalfrom the counter 26, the switch control circuit 28 generates a controlsignal which is applied through a line 31 to the switch 3 so as toconnect the terminal 7 to the terminal 4. Accordingly, the instantaneouslevel of the output signal of the amplifier llb is reduced and againintersects with the zero-level O at a time T delayed by a time t fromthe time T At the same time T the state of the multivibrator 24a isrestored so that the counter 26 starts to count the number of pulsesfrom the pulse generator 25 while the switch control circuit 28 switchesoff the switch 13 and switches the terminal 7 of the switch 3 to theterminal 6 to obtain the stationary condition. The counter 26 countsover m pulses during the time t,, and generates a digital outputrepresentative of the m pulses. After an appropriate time from the timeT the switch control circuit 28 generates a control signal to switch-onthe switch 13 and to switch the terminal 7 of the switch 3 to theterminal 5. Accordingly, the output wave form W2 is obtained at theoutput terminal 12 of the amplifier llb. As seen from the waveforms wand W2 in FIG. 12, the amplifier llb has a suflieiently high gain sothat the amplifier llb is saturated at a low level ofthe output signalw, ofthe integrator. The abovementioned operations are repeated.

In accordance with the above-operations, the following result isobtained.

By way of example, if it is assumed that the time 1 is a time in whichone thousand pulses are generated from the pulse generator, that thereference voltage V, of the reference d-c source 22 is l volt and thatthe counter 26 counts 542 pulses in the time t the value V, of the inputsignal is 0.542 volts.

if the input signal V,- has minus polarity, the polarity of thereference d-c voltage source 22 is also reversed so that plus terminalof the source 22 is connected to the terminal 4. The polarity of theoutput terminal of the d-c amplifier 11b may have the I: same] reversepolarity [as] to the input terminal of the amplifier llb. [n this case,the [phase] polarity relationship between the input and output terminalsof the d-c amplifier I9 is I: also reversed the same polarity. in thedrift memory circuit 20, the d-c amplifier 19 may be inserted in theline 18 so that the switch 13 is connected to the terminal 12 and theoutput terminal of the d-c amplifier 19 is connected to the inputterminal 10b of the amplifier 11 through the line 18.

The embodiment shown in FIG. 11 can be modified as shown in FlG. 14 inwhich a d-c amplifier 21 is fur ther provided between the commonterminal 7 and the integrating resistor 8. Other parts are the same asthe embodiment shown in FIG. 11. A time chart explanatory oftheoperation of the example in FIG. 14 is shown in FIG. 15.

In operation, the common terminal 7 of the switch 3 is connected to theterminal 6 while the switch 13 is switched-on. in this case, if it isassumed that the respective drift voltages of the d-c amplifiers 21, 1la, 11b and 19 converted in terms of the respective [inputs inputterminals are values V V V and V the output V,, of the output terminal12 is as follows:

where references u,, u U3 and u are respective amplification factors ofthe amplifiers 21, 11a, 11b and 19. if a condition u u u I is applied tothe Equation (23 the following result is obtained.

Therefore, a voltage V of the input terminal 10b of the amplifier 11b isindicated as follows:

lf a condition u u u 1 and a condition u I are applied to the Equation(25), the following result is obtained.

Accordingly, no current flows in the integrating resistor 8. Moreover, avoltage V of the input terminal of the d-c amplifier 11b is indicated asfollows:

a: 0 4 4 4 l l 2) 2 (2 If a condition u u u 1 is applied to the Equation[27), the following result is obtained.

As understood from the above equation, drift voltages of the d-camplifiers 21,1la and 11b can be effectively eliminated in theembodiment shown in FIG. 14. In

other words, drift voltages of the preceding amplifier 21 and thesucceeding amplifier 11b can be eliminated in addition to the driftvoltage of the integrator (8, 9 and 11a).

The embodiment shown in FIG. 14 can be applied to form ananalogue-digital converter as shown in FIG. 16. The operation of theanalogue digital converter shown in H6. 16 can be understood in view ofthe operation of the analogue-digital converter shown in FIG. 13.Therefore, details are omitted while waveforms w and W2" are respectiveoutputs of the amplifiers 11a and llb. As seen from the waveforms w andW2 in FIG. 15, the amplifier 11b has a sufficiently high gain so thatthe amplifier llh is saturated at a low level ofthe output signal W1 0fthe integrator.

What I claim is:

1. An integrating network comprising:

an integrator having an output and having an input for receiving aninput voltage signal, and being formed by a first d-c amplifier andtime'constant means connected to said first d-c amplifier,

drift memory circuit means connected between the output and input of theintegrator for feeding back in the opposite polarity] the output of thefirst d-c amplifier to [the] an input of the integrator in the absenceof an input voltage at an input of the first d-c amplifier so as toobtain a stationary condition and for continuously sending out, as afeedback signal, a voltage fed back to the input of the integrator atthe stationary condition, the feedback signal having a valuesubstantially equal to the drift voltage of the first d-c amplifierconverted in terms of the input of the integrator,

whereby an input voltage signal is integrated in the integrator withouterror caused by the drift of the first d-c amplifier,

level detector means connected to the output of the integrator toproduce a first control pulse when the output of the integrator exceedsa predetermined reference level and to produce a second control pulsewhen the output of the integrator crosses the predetermined referencelevel in the decreasing direction,

a time measuring means coupled to the level detector for generating athird control pulse in response to the termination of a predeterminedfirst time period measured from the first control pulse and formeasuring a second time period between the third control pulse and thesecond control pulse,

a reference d-c source, and

input switch means connected to said reference d-c source and to theinput of the integrator for applying the input voltage signal to theintegrator in response to the first control pulse, for applying areference d-c voltage from the d-c source to the integrator in responseto the third control pulse, and for shortening the input of theintegrator in response to the second control pulse,

whereby the level of the input voltage signal can be determined by theratio of the second time period to the first time period, multiplied bythe value of the reference voltage from the reference d-c source.

2. An integrating network according to claim I, in which the driftmemory circuit means comprises a second d-c amplifier, a switchconnected to the output of the second d-c amplifier, means for actuatingsaid switch to a closed state in the absence of said input voltage atthe input of the first d-c amplifier and for actuating said switch to anopen state upon application of the input voltage to the first d-camplifier. and a capacitor connected in series between the switch andground. 3. An integrating network according to claim 1, in which thedrift memory circuit means comprises a switch, and means for actuatingsaid switch to a switched-on state in the absence of said input voltageat the first d-c amplifier, and to a switched-off state at theapplication of the input voltage to the dc first amplifier, a capacitorconnected between the switch and ground, and a second d-c amplifierconnected to the junction between the switch and the capacitor.

4. An integrating network according to claim 1, in which the first d-camplifier is a differential amplifier having a first input terminalreceiving the input voltage signal to be integrated and a second inputterminal receiving the feedback signal.

5. An integrating network, comprising: an integrator having an input andan output, and

being formed by a first d-c amplifier and timeconstant means connectedto said first d-c amplifier, 1

a second d-c amplifier having an output connected to said input of theintegrator, and having an input for the application of an input voltagesignal thereto,

drift memory circuit means connected between the output and input of theintegrator for feeding back [in the opposite polarity] the output of thefirst d-c amplifier to [the] an input of the integrator in the absenceof said input voltage at an input of the second d-c amplifier so as toestablish a quiescent condition and for continuously sending out, as afeedback signal, a voltage fed back to the input of the integrator atthe quiescent condition, the feedback signal having a valuesubstantially equal to the drift voltages of the first and second d-camplifiers converted in terms of the input of the integrator,

whereby said input voltage signal applied through the second d-camplifier is integrated without error caused by the drift of the firstand second d-c amplifiers.

6. An integrating network according to claim 5, in which the driftmemory circuit means comprises a third d-c amplifier, a switch connectedto the output of the third d-c amplifier, means for actuating saidswitch to a closed state in the absence of said input voltage at theinput of the first d-c amplifier and for actuating said switch to anopen state upon application of the input voltage to the first d-camplifier, and a capacitor connected in series between the switch andground.

7. An integrating network according to claim 5, in which the driftmemory circuit means comprises a switch, and means for actuating saidswitch to a switchon state in the absence of said input voltage at thefirst d-c amplifier. and to a switched-off state at the application ofthe input voltage to the d-c first amplifier, a capacitor connectedbetween the switch and ground, and a third d-c amplifier connected tothe junction between the switch and the capacitor.

8. An integrating network according to claim 5, in which the first d-camplifier is a differential amplifier having a first input terminalreceiving the input voltage signal to be integrated and a second inputterminal re ceiving the feedback signal.

9. An integrating network, comprising:

an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connectedto said first d-c amplifier,

a second d-c amplifier having an output connected to said input of theintegrator, and

drift memory circuit means connected between the output and input of theintegrator for feeding back I: in the opposite polarity the output ofthe first d-c amplifier to [the] an input of the integrator in theabsence of an input voltage at an input of the second d-c amplifier soas to obtain a stationary condition and for continuously sending out, asa feedback signal, a voltage fed back to the input of the integrator atthe stationary condition, the feedback signal having a valuesubstantially equal to the drift voltages of the first and second d-camplifiers converted in terms of the input of the integrator,

whereby an input voltage signal applied through the second d-c amplifieris integrated without error caused by the drift of the first and secondd-c amplifiers,

level detector means connected to the output of the integrator toproduce a first control pulse when the output of the integrator exceedsa predetermined reference level and to produce a second control pulsewhen the output of the integrator crosses the predetermined referencelevel on the decreasing direction,

a time measuring means coupled to the level detector for generating athird control pulse in response to the termination of a predeterminedfirst time period measured from the first control pulse and formeasuring a second time period between the third control pulse and thesecond control pulse,

a reference d c source, and

input switch means connected to said reference d-c source and to theinput of the second d-c amplifier for applying the input voltage signalto the second d-c amplifier in response to the first control pulse, forapplying a reference d-c voltage from the d-c source to the second d-camplifier in response to the third control pulse, and for shorting theinput of the second d-c amplifier in response to the second controlpulse,

whereby the level of the input voltage signal can be determined by theratio of the second time period to the first time period, multiplied bythe value of the reference voltage of the d-c source.

10. An integrating network, comprising:

an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connectedto said first d-c amplifier,

a second d-c amplifier having an input connected to said output of theintegrator, and

drift memory circuit means connected between the output of the secondamplifier and the input of the integrator for feeding back [in theopposite polarity] the output of the second dc amplifier to [the] aninput of the integrator in the absence of an input voltage at the inputof the first d-c amplifier so as to obtain a stationary condition andfor continuously sending out, as a feedback signal, a voltage fed backto the input of the integrator at the stationary condition, the fed backsignal having a value substantially equal to the drift voltages of thefirst and second d-c amplifiers converted in terms of the input of theintegrator,

whereby an input voltage is integrated in the integrator without errorcaused by the drift of the first and second d-c amplifiers so as toproduce an integrated output of the input voltage at the output of thesecond amplifier.

level detector means connected to the output of the second d-c amplifierto produce a first control pulse when the output of the second d-camplifier exceeds a predetermined reference level and to produce asecond control pulse when the output of the second d-c amplifier crossesthe predetermined reference level in the decreasing direction,

a time measuring means coupled to the level detector for generating athird control pulse in response to the termination of a predeterminedfirst time period measured from the first control pulse and formeasuring a second time period between the third control pulse and thesecond control pulse,

a reference d-c source, and

input switch means connected to said reference d-c source and to theinput of the integrator for applying the input voltage signal to theintegrator in response to the first control pulse, for applying areference d-c voltage from the d-c source to the inte grator in responseto the third control pulse, and for shorting the input of the integratorin response to the second control pulse,

whereby the level of the input voltage signal can be determined by theratio of the second time period to the first time period, multiplied bythe value of the reference voltage from the reference d-c source,

11. An integrating network, comprising:

an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connectedto the first d-c amplifier,

a second d-c amplifier having an output connected to said input of theintegrator,

a third d-c amplifier having an input connected to the output of theintegrator, and

drift memory circuit means connected between the output of the thirdamplifier and the input of the integrator for feeding back in theopposite polarity the output of the third d-c amplifier to [the] aninput of the integrator in the absence of an input voltage at the inputof the second d-c amplifier so as to obtain a stationary condition andfor continuously sending out, as a feedback signal, a voltage fed backto the input of the integrator at the stationary condition, the fed backsignal having a value substantially equal to the drift voltages of thefirst, second and third d-c amplifiers converted in terms of the inputof the integrator,

whereby an input voltage signal applied through the second d-c amplifieris integrated in the integrator without error caused by the drift of thefirst, second and third d-c amplifiers so as to produce an integratedoutput of the input voltage at the output of the third amplifier,

level detector means connected to the output of the third d-c amplifierto produce a first control pulse when the output of the third theamplifier exceeds a predetermined reference level and to produce asecond control pulse when the output of the third d-c amplifier crossesthe predetermined reference level in the decreasing direction,

a time measuring means coupled to the level detector for generating athird control pulse in response to the termination of a predeterminedfirst time per iod measured from the first control pulse and formeasuring a second time period between the third control pulse and thesecond control pulse,

a reference d-c source, and

input switch means connected to said reference d-c source and to theinput of the second d-c amplifier for applying the input voltage signalto the second d-c amplifier in response to the first control pulse, forapplying a reference d-c voltage from the dc source to the second d-camplifier in response to the third control pulse, and for shorting theinput of the second d-c amplifier in response to the second controlpulse,

whereby the level of the input voltage signal can be determined by theratio of the second time period to the first time period, multiplied bythe value of the reference voltage from the reference d-c source.

12. An integrating network, comprising:

an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connectedto said first d-c amplifier,

a second d-c amplifier having an input connected to said output of theintegrator, and

drift memory circuit means connected between the output of the secondamplifier and the input of the integrator for feeding back [in theopposite polarity] the output of the second d-c amplifier to [the] aninput of the integrator in the absence of an input voltage at the inputof the first d-c amplifier so as to obtain a stationary condition andfor continuously sending out, as a feedback signal, a voltage fed backto the input of the integrator at the stationary condition, the fed backsignal having a value substantially equal to the drift voltages of thefirst and second d-c amplifiers converted in terms of the input of theintegrator,

whereby an input voltage is integrated in the integrator without errorcaused by the drift of the first and second d-c amplifiers so as toproduce an integrated output of the input voltage at the output of thesecond amplifier,

13. An integrating network according to claim 12, in which the driftmemory circuit means comprises a third d-c amplifier, a switch connectedto the output of the third d-c amplifier, means for actuating saidswitch to a closed state in the absence of said input voltage at theinput of the first d c amplifier and for actuating said switch to anopen state upon application of the input voltage to the first d-camplifier, and a capacitor connected in series between the switch andground.

14. An integrating network according to claim 12, in which the driftmemory circuit means comprises a switch, and means for actuating saidswitch to a switched-on state in the absence of said input voltage atthe first d-c amplifier, and to a switched-off state at the applicationof the input voltage to the first d-c amplifier, a capacitor connectedbetween the switch and ground, and a third d-c amplifier connected tothe junction between the switch and the capacitor.

15. An inte rating network according to claim 12, in which thefcomprising an integrator having an input terminal and an outputterminal and being formed by a first d-c amplifier and time-constantmeans connected to the first d-c amplifier, said first d-c amplifier I:is] being a differential amplifier having a first input terminalreceiving [the] an input voltage signal to be integrated and a secondinput terminal, [receiving the feedback signal] a second d-c amplifierhaving an input terminal connected to the output terminal of theintegrator,

drift memory circuit means connected between an output terminal ofsaidsecond d-c amplifier and the second input terminal of said differentialamplifier for feeding back the output of the second d-c amplifier tosaid second input terminal of said differential amplijier in the absenceof said input voltage signal at the input terminal ofthe integrator soas to establish a quiescent condition, the feedback signal having avalue substantially equal to the drift voltage of the first and secondd-c amplifier converted to terms of the first input terminal of saiddifferential amplifier,

whereby said input voltage signal is integrated in the integratorwithout error caused by the drift of the first and second d-c amplifierso as to produce an integrated and amplified output of the input voltageat the output terminal of the second amplifier.

16. An integrating network, comprising:

an integrator having an input and an output, and

being formed by a first d-c amplifier and timeconstant means connectedto the first cl-c amplifier,

a second d-c amplifier having an output connected to said input of theintegrator, and having an input for the application of an input voltagesignal,

a third d-c amplifier having an input connected to the output of theintegrator, and drift memory circuit means connected between the outputof the third amplifier and the input of the integrator for feeding backin the opposite polarity] the output of the third d-c amplifier to [the]an input of the integrator in the absence of said input voltage at theinput of the' second d-c amplifier so as to establish a quienscentcondition and for continuously sending out, as a feedback signal, avoltage fed back to the input of the integrator at the quiescentcondition, the fed back signal having a value substantially equal to thedrift voltages of the first, second and third d-c amplifiers convertedin terms of the input of the integrator,

whereby said input voliage signal applied through the second d-camplifier is integrated in the integrator without error caused by thedrift of the first, second and third d-c amplifiers so as to produce anintegrated output of the input voltage at the output of the thirdamplifier.

17. An integrating network according to claim 16, in which the driftmemory circuit means comprises a fourth d-c amplifier, a switchconnected to the output of the fourth d-c amplifier, means for actuatingsaid switch to a closed state in the absence of said input voltage atthe input of the first d-c amplifier and for actuating said switch to anopen state upon application of the input voltage to the first d-camplifier, and a capacitor connected in series between the switch andground.

18. An integrating network according to claim 16, in which the driftmemory circuit means comprises a switch, and means for actuating saidswitch to a switched-on state in the absence of said input voltage atthe first d-c amplifier, and to a switched-off state at the applicationof the input voltage to the d-c first amplifier, a capacitor connectedbetween the switch and ground, and a fourth d-c amplifier connected tothe junction between the switch and the capacitor.

19. An integrating network [according to claim 16, in which the]comprising an integrator having an input terminal and an output terminaland being formed by a first d-c amplifier and time-constant meansconnected to the first d-c amplifier,

a second d-c amplifier having an output terminal connected to said inputterminal of the integrator and an input terminalfor the application ofaninput voltage signal, said first d-c amplifier [is] being a differentialamplifier having a first input terminal receiving the input voltagesignal [to be integrated receiving, through said second d-c amplifier,said input voltage signal and a second input terminal, [receiving thefeedback signal] third d-c amplifier having an input terminal connectedto the output terminal of the integrator,

drift memory circuit means connected between an output terminal ofsaidthird d-c amplifier and the sec and input terminal of said differentialamplifier for feeding back the output of the third d-c amplifier to saidsecond input terminal ofsaid differential amplifier in the absenceofsaid input voltage signal at the input terminal of the second d-camplifier so as to establish a quiescent condition and for continuouslysending out, as afeedback signal, a voltage fed back to said secondinput terminal ofsaid differential am plifier at the quiescentcondition, the feedback signal having a value substantially equal to thedrift voltage ofthe first, second and third amplifiers converted interms of the first input terminal of said differential amplifier,

whereby said input voltage signal applied through the second d-camplifier is integrated in the integrator without error caused by thedrift of the first, second and third d-c amplifiers so as to produce anintegrated and amplified output of the input voltage at the outputterminal of the third amplifier.

20. An integrating network according to claim I5, in which said secondd-c amplifier is saturable at a low level of the output of saidintegrator.

21. An integrating network according to claim 19, in which said secondd-c amplifier is saturable at a low level of the output of saidintegrator.

UNITED STATES PATENT OFFICE QERTIFICATE OF CORRECTION PATENT NO. 2 Re.28,579

DATED Reissued Oct. 21, 1975 INVENTOR(S) 1 Kozo Uchida It is certifiedthat error appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

Column ll, line 20, delete "ll" and insert --lla-;

Column 17, line 46, delete "fed back" and insert --feedback--;

Column 18, line 56, delete "second" and insert -third--.

Signed and Scaled this eighth Day of June 1976 [SEAL] Arrest:

RUTH C. MASON C. MARSHALL DANN m?" I fimnlimoner oj'Pamm and Trademark:

1. An integrating network comprising: an integrator having an output andhaving an input for receiving an input voltage signal, and being formedby a first d-c amplifier and time-constant means connected to said firstd-c amplifier, drift memory circuit means connected between the outputand input of the integrator for feeding back (in the opposite polarity)the output of the first d-c amplifier to (the) an input of theintegrator in the absence of an input voltage at an input of the firstd-c amplifier so as to obtain a stationary condition and forcontinuously sending out, as a feedback signal, a voltage fed back tothe input of the integrator at the stationary condition, the feedbacksignal having a value substantially equal to the drift voltage of thefirst d-c amplifier converted in terms of the input of the integrator,whereby an input voltage signal is integrated in the integrator withouterror caused by the drift of the first d-c amplifier, level detectormeans connected to the output of the integrator to produce a firstcontrol pulse when the output of the integrator exceeds a predeterminedreference level and to produce a second control pulse when the output ofthe integrator crosses the predetermined reference level in thedecreasing direction, a time measuring means coupled to the leveldetector for generating a third control pulse in response to thetermination of a predetermined first time period measured from the firstcontrol pulse and for measuring a second time period between the thirdcontrol pulse and the second control pulse, a reference d-c source, andinput switch means connected to said reference d-c source and to theinput of the integrator for applying the input voltage signal to theintegrator in response to the first control pulse, for applying areference d-c voltage from the d-c source to the integrator in responseto the third control pulse, and for shortening the input of theintegrator in response to the second control pulse, whereby the level ofthe input voltage signal can be determined by the ratio of the secondtime period to the first time period, multiplied by the value of thereference voltage from the reference d-c source.
 2. An integratingnetwork according to claim 1, in which the drift memory circuit meanscomprises a second d-c amplifier, a switch connected to the output ofthe second d-c amplifier, means for actuating said switch to a closedstate in the absence of said input voltage at the input of the first d-camplifier and for actuating said switch to an open state uponapplication of the input voltage to the first d-c ampLifier, and acapacitor connected in series between the switch and ground.
 3. Anintegrating network according to claim 1, in which the drift memorycircuit means comprises a switch, and means for actuating said switch toa switched-on state in the absence of said input voltage at the firstd-c amplifier, and to a switched-off state at the application of theinput voltage to the d-c first amplifier, a capacitor connected betweenthe switch and ground, and a second d-c amplifier connected to thejunction between the switch and the capacitor.
 4. An integrating networkaccording to claim 1, in which the first d-c amplifier is a differentialamplifier having a first input terminal receiving the input voltagesignal to be integrated and a second input terminal receiving thefeedback signal.
 5. An integrating network, comprising: an integratorhaving an input and an output, and being formed by a first d-c amplifierand time-constant means connected to said first d-c amplifier, a secondd-c amplifier having an output connected to said input of theintegrator, and having an input for the application of an input voltagesignal thereto, drift memory circuit means connected between the outputand input of the integrator for feeding back (in the opposite polarity)the output of the first d-c amplifier to (the) an input of theintegrator in the absence of said input voltage at an input of thesecond d-c amplifier so as to establish a quiescent condition and forcontinuously sending out, as a feedback signal, a voltage fed back tothe input of the integrator at the quiescent condition, the feedbacksignal having a value substantially equal to the drift voltages of thefirst and second d-c amplifiers converted in terms of the input of theintegrator, whereby said input voltage signal applied through the secondd-c amplifier is integrated without error caused by the drift of thefirst and second d-c amplifiers.
 6. An integrating network according toclaim 5, in which the drift memory circuit means comprises a third d-camplifier, a switch connected to the output of the third d-c amplifier,means for actuating said switch to a closed state in the absence of saidinput voltage at the input of the first d-c amplifier and for actuatingsaid switch to an open state upon application of the input voltage tothe first d-c amplifier, and a capacitor connected in series between theswitch and ground.
 7. An integrating network according to claim 5, inwhich the drift memory circuit means comprises a switch, and means foractuating said switch to a switch-on state in the absence of said inputvoltage at the first d-c amplifier, and to a switched-off state at theapplication of the input voltage to the d-c first amplifier, a capacitorconnected between the switch and ground, and a third d-c amplifierconnected to the junction between the switch and the capacitor.
 8. Anintegrating network according to claim 5, in which the first d-camplifier is a differential amplifier having a first input terminalreceiving the input voltage signal to be integrated and a second inputterminal receiving the feedback signal.
 9. An integrating network,comprising: an integrator having an input and an output, and beingformed by a first d-c amplifier and time-constant means connected tosaid first d-c amplifier, a second d-c amplifier having an outputconnected to said input of the integrator, and drift memory circuitmeans connected between the output and input of the integrator forfeeding back (in the opposite polarity) the output of the first d-camplifier to (the) an input of the integrator in the absence of an inputvoltage at an input of the second d-c amplifier so as to obtain astationary condition and for continuously sending out, as a feedbacksignal, a voltage fed back to the input of the integrator at thestationary condition, the feedback signal havIng a value substantiallyequal to the drift voltages of the first and second d-c amplifiersconverted in terms of the input of the integrator, whereby an inputvoltage signal applied through the second d-c amplifier is integratedwithout error caused by the drift of the first and second d-camplifiers, level detector means connected to the output of theintegrator to produce a first control pulse when the output of theintegrator exceeds a predetermined reference level and to produce asecond control pulse when the output of the integrator crosses thepredetermined reference level in the decreasing direction, a timemeasuring means coupled to the level detector for generating a thirdcontrol pulse in response to the termination of a predetermined firsttime period measured from the first control pulse and for measuring asecond time period between the third control pulse and the secondcontrol pulse, a reference d-c source, and input switch means connectedto said reference d-c source and to the input of the second d-camplifier for applying the input voltage signal to the second d-camplifier in response to the first control pulse, for applying areference d-c voltage from the d-c source to the second d-c amplifier inresponse to the third control pulse, and for shorting the input of thesecond d-c amplifier in response to the second control pulse, wherebythe level of the input voltage signal can be determined by the ratio ofthe second time period to the first time period, multiplied by the valueof the reference voltage of the d-c source.
 10. An integrating network,comprising: an integrator having an input and an output, and beingformed by a first d-c amplifier and time-constant means connected tosaid first d-c amplifier, a second d-c amplifier having an inputconnected to said output of the integrator, and drift memory circuitmeans connected between the output of the second amplifier and the inputof the integrator for feeding back (in the opposite polarity) the outputof the second d-c amplifier to (the) an input of the integrator in theabsence of an input voltage at the input of the first d-c amplifier soas to obtain a stationary condition and for continuously sending out, asa feedback signal, a voltage fed back to the input of the integrator atthe stationary condition, the fed back signal having a valuesubstantially equal to the drift voltages of the first and second d-camplifiers converted in terms of the input of the integrator, whereby aninput voltage is integrated in the integrator without error caused bythe drift of the first and second d-c amplifiers so as to produce anintegrated output of the input voltage at the output of the secondamplifier, level detector means connected to the output of the secondd-c amplifier to produce a first control pulse when the output of thesecond d-c amplifier exceeds a predetermined reference level and toproduce a second control pulse when the output of the second d-camplifier crosses the predetermined reference level in the decreasingdirection, a time measuring means coupled to the level detector forgenerating a third control pulse in response to the termination of apredetermined first time period measured from the first control pulseand for measuring a second time period between the third control pulseand the second control pulse, a reference d-c source, and input switchmeans connected to said reference d-c source and to the input of theintegrator for applying the input voltage signal to the integrator inresponse to the first control pulse, for applying a reference d-cvoltage from the d-c source to the integrator in response to the thirdcontrol pulse, and for shorting the input of the integrator in responseto the second control pulse, whereby the level of the input voltagesignal can be determined by the ratio of the second time period to thefirst time period, multiplieD by the value of the reference voltage fromthe reference d-c source.
 11. An integrating network, comprising: anintegrator having an input and an output, and being formed by a firstd-c amplifier and time-constant means connected to the first d-camplifier, a second d-c amplifier having an output connected to saidinput of the integrator, a third d-c amplifier having an input connectedto the output of the integrator, and drift memory circuit meansconnected between the output of the third amplifier and the input of theintegrator for feeding back (in the opposite polarity) the output of thethird d-c amplifier to (the) an input of the integrator in the absenceof an input voltage at the input of the second d-c amplifier so as toobtain a stationary condition and for continuously sending out, as afeedback signal, a voltage fed back to the input of the integrator atthe stationary condition, the fed back signal having a valuesubstantially equal to the drift voltages of the first, second and thirdd-c amplifiers converted in terms of the input of the integrator,whereby an input voltage signal applied through the second d-c amplifieris integrated in the integrator without error caused by the drift of thefirst, second and third d-c amplifiers so as to produce an integratedoutput of the input voltage at the output of the third amplifier, leveldetector means connected to the output of the third d-c amplifier toproduce a first control pulse when the output of the third d-c amplifierexceeds a predetermined reference level and to produce a second controlpulse when the output of the third d-c amplifier crosses thepredetermined reference level in the decreasing direction, a timemeasuring means coupled to the level detector for generating a thirdcontrol pulse in response to the termination of a predetermined firsttime period measured from the first control pulse and for measuring asecond time period between the third control pulse and the secondcontrol pulse, a reference d-c source, and input switch means connectedto said reference d-c source and to the input of the second d-camplifier for applying the input voltage signal to the second d-camplifier in response to the first control pulse, for applying areference d-c voltage from the d-c source to the second d-c amplifier inresponse to the third control pulse, and for shorting the input of thesecond d-c amplifier in response to the second control pulse, wherebythe level of the input voltage signal can be determined by the ratio ofthe second time period to the first time period, multiplied by the valueof the reference voltage from the reference d-c source.
 12. Anintegrating network, comprising: an integrator having an input and anoutput, and being formed by a first d-c amplifier and time-constantmeans connected to said first d-c amplifier, a second d-c amplifierhaving an input connected to said output of the integrator, and driftmemory circuit means connected between the output of the secondamplifier and the input of the integrator for feeding back (in theopposite polarity) the output of the second d-c amplifier to (the) aninput of the integrator in the absence of an input voltage at the inputof the first d-c amplifier so as to obtain a stationary condition andfor continuously sending out, as a feedback signal, a voltage fed backto the input of the integrator at the stationary condition, the fed backsignal having a value substantially equal to the drift voltages of thefirst and second d-c amplifiers converted in terms of the input of theintegrator, whereby an input voltage is integrated in the integratorwithout error caused by the drift of the first and second d-c amplifiersso as to produce an integrated output of the input voltage at the outputof the second amplifier.
 13. An integrating network according to claim12, in which the drift memory circuit means comprises a third d-camplifier, a switch connected to the output of the third d-c amplifier,means for actuating said switch to a closed state in the absence of saidinput voltage at the input of the first d-c amplifier and for actuatingsaid switch to an open state upon application of the input voltage tothe first d-c amplifier, and a capacitor connected in series between theswitch and ground.
 14. An integrating network according to claim 12, inwhich the drift memory circuit means comprises a switch, and means foractuating said switch to a switched-on state in the absence of saidinput voltage at the first d-c amplifier, and to a switched-off state atthe application of the input voltage to the first d-c amplifier, acapacitor connected between the switch and ground, and a third d-camplifier connected to the junction between the switch and thecapacitor.
 15. An integrating network (according to claim 12, in whichthe) comprising an integrator having an input terminal and an outputterminal and being formed by a first d-c amplifier and time-constantmeans connected to the first d-c amplifier, said first d-c amplifier(is) being a differential amplifier having a first input terminalreceiving (the) an input voltage signal to be integrated and a secondinput terminal, (receiving the feedback signal) a second d-c amplifierhaving an input terminal connected to the output terminal of theintegrator, drift memory circuit means connected between an outputterminal of said second d-c amplifier and the second input terminal ofsaid differential amplifier for feeding back the output of the secondd-c amplifier to said second input terminal of said differentialamplifier in the absence of said input voltage signal at the inputterminal of the integrator so as to establish a quiescent condition, thefeedback signal having a value substantially equal to the drift voltageof the first and second d-c amplifier converted to terms of the firstinput terminal of said differential amplifier, whereby said inputvoltage signal is integrated in the integrator without error caused bythe drift of the first and second d-c amplifier so as to produce anintegrated and amplified output of the input voltage at the outputterminal of the second amplifier.
 16. An integrating network,comprising: an integrator having an input and an output, and beingformed by a first d-c amplifier and time-constant means connected to thefirst d-c amplifier, a second d-c amplifier having an output connectedto said input of the integrator, and having an input for the applicationof an input voltage signal, a third d-c amplifier having an inputconnected to the output of the integrator, and drift memory circuitmeans connected between the output of the third amplifier and the inputof the integrator for feeding back (in the opposite polarity) the outputof the third d-c amplifier to (the) an input of the integrator in theabsence of said input voltage at the input of the second d-c amplifierso as to establish a quienscent condition and for continuously sendingout, as a feedback signal, a voltage fed back to the input of theintegrator at the quiescent condition, the fed back signal having avalue substantially equal to the drift voltages of the first, second andthird d-c amplifiers converted in terms of the input of the integrator,whereby said input voltage signal applied through the second d-camplifier is integrated in the integrator without error caused by thedrift of the first, second and third d-c amplifiers so as to produce anintegrated output of the input voltage at the output of the thirdamplifier.
 17. An integrating network according to claim 16, in whichthe drift memory circuit means comprises a fourth d-c amplifier, aswitch connected to the output of the fourth d-c amplifier, means foractuating said switch to a closed state in the absence of said inputvoltage at the input of the first d-c amplifier and for actuating saidswitch to an open state upon application of the input voltage to thefirst d-c amplifier, and a capacitor connected in series between theswitch and ground.
 18. An integrating network according to claim 16, inwhich the drift memory circuit means comprises a switch, and means foractuating said switch to a switched-on state in the absence of saidinput voltage at the first d-c amplifier, and to a switched-off state atthe application of the input voltage to the d-c first amplifier, acapacitor connected between the switch and ground, and a fourth d-camplifier connected to the junction between the switch and thecapacitor.
 19. An integrating network (according to claim 16, in whichthe) comprising an integrator having an input terminal and an outputterminal and being formed by a first d-c amplifier and time-constantmeans connected to the first d-c amplifier, a second d-c amplifierhaving an output terminal connected to said input terminal of theintegrator and an input terminal for the application of an input voltagesignal, said first d-c amplifier (is) being a differential amplifierhaving a first input terminal receiving the input voltage signal (to beintegrated) receiving, through said second d-c amplifier, said inputvoltage signal and a second input terminal, (receiving the feedbacksignal) a third d-c amplifier having an input terminal connected to theoutput terminal of the integrator, drift memory circuit means connectedbetween an output terminal of said third d-c amplifier and the secondinput terminal of said differential amplifier for feeding back theoutput of the third d-c amplifier to said second input terminal of saiddifferential amplifier in the absence of said input voltage signal atthe input terminal of the second d-c amplifier so as to establish aquiescent condition and for continuously sending out, as a feedbacksignal, a voltage fed back to said second input terminal of saiddifferential amplifier at the quiescent condition, the feedback signalhaving a value substantially equal to the drift voltage of the first,second and third amplifiers converted in terms of the first inputterminal of said differential amplifier, whereby said input voltagesignal applied through the second d-c amplifier is integrated in theintegrator without error caused by the drift of the first, second andthird d-c amplifiers so as to produce an integrated and amplified outputof the input voltage at the output terminal of the third amplifier. 20.An integrating network according to claim 15, in which said second d-camplifier is saturable at a low level of the output of said integrator.21. An integrating network according to claim 19, in which said secondd-c amplifier is saturable at a low level of the output of saidintegrator.